CPU:
- IA 64, HotChips 11
- The incredible Shrinking CPU
- MP Systems- Coherency
- Sandy Bridge MicroArchitecture
- Sandy Bridge CPU Architecture
- Haswell MicroArchitecture
- Haswell Transactional Memory
- Nehalem –> Skylake
- Sandy Bridge Micro Architecture - HotChips 23
- Ivy Bridge Micro Architecture - HotChips 24
- Skylake Micro Architecture - HotChips 28
- The Pentium Chronicles
- AMD K6, K6-2 and K6-III CPU resource
- Spectre & Meltdown, HotChips 30
- RiscV, HotChips 31
- Intel Lakefield, HotChips 31
- Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution
MultiCore & stuff:
- Part1: Threads, DataRaces, Deadlocks & Livelocks
- Part2: Heavily Contended Locks
- Part3: Nonblocking Algos
- Part4: Memory, Cache Consistency
- MultiCore Programming Practices Guide
- MultiCore Processing in Context-1
- MultiCore Processing in Context-2
- In pursuit of faster futexes
- Intel Quickpath connect architecture
Intel 80386 Raymond Chen:
- The Intel 80386, part 1: Introduction
- The Intel 80386, part 2: Memory addressing modes
- The Intel 80386, part 3: Flags and condition codes
- The Intel 80386, part 4: Arithmetic
- The Intel 80386, part 5: Logical operations
- The Intel 80386, part 6: Data transfer instructions
- The Intel 80386, part 7: Conditional instructions and control transfer
- The Intel 80386, part 8: Block operations
- The Intel 80386, part 9: Stack frame instructions
- The Intel 80386, part 10: Atomic operations and memory alignment
- The Intel 80386, part 11: The TEB
- The Intel 80386, part 12: The stuff you don’t need to know
- The Intel 80386, part 13: Calling conventions
- The Intel 80386, part 14: Rescuing a stack trace after the debugger gave up when it reached an FPO function
- The Intel 80386, part 15: Common compiler-generated code sequences
- The Intel 80386, part 16: Code walkthrough